Cadence Design Systems, announced that its digital and custom/analog flows achieved certification for Samsung Foundry’s SF2 and SF3 process technologies. The two companies also worked together to create new process design kits (PDKs) that simplify mobile, automotive, AI, and hyper-scale IC design at these latest nodes. Joint customers are actively developing SF2- and SF3-based designs using the Cadence flows.
Cadence’s comprehensive Cadence RTL-to-GDS design flow that supports Samsung’s SF2 and SF3 technologies provides optimal power, performance, and area (PPA). The flow includes the Genus Synthesis Solution, Modus DFT Software Solution, Innovus Implementation System, Quantus Extraction Solution and Quantum Field Solver, Tempus Timing Signoff Solution and Tempus ECO Option, Pegasus Verification System, Liberate Characterization Portfolio, Voltus IC Power Integrity Solution and the Cadence Cerebrus Intelligent Chip Explorer.
With the certified flow, customers have access to several features that ease IC design at advanced nodes, such as cell-swapping support, which helps designers align cell pins for direct connections to conserve routing resources; support for mixed-row solutions in various combinations to maximize area-based design rules; the ability to place and refine traces using mask-shifted cells and horizontal half-track shifted cells to reduce displacement; support for various rectilinear standard cells to achieve higher density; and reduced IR drop due to the insertion of enhanced, trim-aware via staples.
Cadence custom and analog tools optimized for Samsung’s SF3 and SF2 nodes include the AI-based Virtuoso Studio design tools—Virtuoso Schematic Editor, Virtuoso ADE Suite, and Cadence Virtuoso Layout Suite—the Spectre Simulation Platform—Spectre X Simulator, Spectre FX and Spectre RF—as well as the Voltus-XFi Custom Power Integrity Solution.
The custom/analog design tools provide customers with several benefits, such as better corner simulation management, statistical analyses, design centering, and circuit optimization; support for parallel operations on modern compute farms and private and public cloud configurations; better performance and scalability throughout the layout environment; mixed-signal OpenAccess design kits for seamless integration with the Innovus Implementation’s place-and-route engines for improved quality of results; summarized EM-IR information, which highlights violations and details on resistance value, metal layer, width, and length information; and feedback regarding circuit performance and reliability.
“Through our latest collaboration with Cadence, we’ve seen early customers improve productivity with the Cadence-certified design flows and our advanced SF2 and SF3 process technologies,” said Sangyun Kim, vice president of the Foundry Design Technology Team at Samsung Electronics. “With the new PDKs, we’re making it easier for developers of next-generation mobile, automotive, AI, and hyper-scale designs to adopt our technologies and deliver innovations to market faster.”
“The Cadence R&D team worked tirelessly with the Samsung Foundry team to fine-tune our digital and custom/analog flows for Samsung’s SF2 and SF3 process technologies, delivering a wide range of benefits that help customers design much more efficiently,” said Vivek Mishra, corporate vice president in the Digital & Signoff Group at Cadence. “Our digital flow provides PPA advantages, and our custom/analog flow, anchored by Virtuoso Studio, sets a new standard for custom IP creation, enabling our mutual customers to push the boundaries of innovation with Samsung’s SF2 and SF3 process technologies.” The Cadence digital and custom/analog flows support the Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence.
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