Nanusens, a MEMS-within-CMOS solutions provider, will be shipping evaluation samples of its new product line, RF Digital Tunable Capacitors (DTCs), in Q2 2021. These tunable capacitors solve the problem of current 5G antenna solutions that are becoming increasingly power hungry in the higher 5G bands. The key is the very high Q factor of above 100 at 1 GHz and at higher 5G bands to keep power losses very low. The Q factor of most rival products drop down significantly. Nanusens DTCs thus open up the power efficient use of higher 5G bands.
The DTCs are created using the company’s award-winning techniques of creating nanostructure within CMOS using only standard techniques in a CMOS fab so there are no limits on production volumes. Also, because they are created in CMOS, they can be built simultaneously with other structures on a chip, giving a lower BOM. Nanusens won Design Team of the Year at the Elektra Awards for its work on DTC.
The Problems with Current Solutions
The global market for antenna tuners was $514M in 2018 and is forecast to grow to $1200M by 2025 as 5G rolls out. The increasing number of 5G phones means that higher 5G bands will be needed to accommodate the extra traffic. To do this requires additional antennas to be integrated into the phone to handle more 5G bands but, due to them having to be smaller to fit more of them inside the phone, their efficiency decreases. To get the best possible performance from each antenna, each has to be tuned to prevent a mismatch between the RF front end and the antenna that would result in losses. This is done with an antenna tuner -- either a solid-state switch or an RF MEMS tunable capacitor but each approach has its drawbacks.
The problem with solid-state switches is that they have a low Q factor, which is a measure of the performance with higher Q factors being better as these indicate lower losses during operation. Solid-state switching solutions’ low Q factor is due to their ON state (Ron) resistance. This becomes worse as the frequency goes up to the higher 5G bands, which has become a limiting factor in using these higher bands effectively. With RF MEMS tunable capacitors, the issue is poor reliability as they use dielectric. This can suffer from dielectric charging which is the main cause of failure in RF MEMS devices and also limits the peak-to-peak voltages that they can withstand before dielectric breakdown.
Key Performance Parameters
The key factors for DTCs are the Q factor and linearity. The Q factor is above 100 at 1GHz, which matches state-of-the-art RF MEMS solutions and is well above solid-state switching solutions. They also show excellent linearity with more than 90 dBc for IMD3 which is the 5G requirement. Minimum capacitance can be kept very small -- down to Coff of 30 fF for a single capacitor off state (that means a Cmin of 0.45 pF for a 4-bit DTC) and even less for future iterations. Similarly, the capacitance ratio is currently 2 and Nanusens expects to improve on this with the next product iteration to 3.
Solves the Increasing Problem of Parasitics
As device performance approaches ideal performance (very low, off-state capacitance (Coff) and very high Q) and new, allocated frequency bands start to move to the microwave domain, parasitics interconnects will increasingly have a negative impact on performance. Being built using a standard CMOS means that the DTC can be made at the same time and on the same chip as other RF front end components, such as PA, LNA and transceivers, to dramatically reduce interconnect parasitics while making them reconfigurable. These single chip reconfigurable solutions will fit in ultra-small, low profile, low cost WLCSP packages and this integration also reduces the BOM and saves board area compared to competitors’ multi-component solutions.
Standard CMOS
Manufacturing in a standard CMOS fab enables Nanusens devices to benefit from the CMOS economies of scale and thus cost up to 30% less than rival products, which use more expensive silicon-on-insulator/silicon-on-sapphire processes or specific MEMS fabs. Nanusens also enjoys the high yields of CMOS fabs for this product, virtually unlimited production volumes, and the ability to use any CMOS fab. Product production times are those of typical CMOS products, unlike some rivals that take considerably longer as non-standard. This will enable the DTC product rollout to be in 2021.
How the Nanusens Uses Standard CMOS Processes
The Inter Metal Dielectric (IMD) is etched away through the pad openings in the passivation layer using vapour HF (vHF) to create the nano-structures. The holes are then sealed and the chip packaged as necessary. As only standard CMOS processes with minimal post-processing are used and the devices can be directly integrated with active circuitry as required with high yields similar to CMOS devices. This also means that the production is fab-independent.
