Analog Devices has introduced an ultra-low jitter synthesizer that operates from 800 MHz to 12.8 GHz for high-performance wideband data converter and synchronization applications. The new ADF4377 synthesizer enables excellent signal-to-noise performance by providing an ultra-clean clock source to drive the signal sampling process. This allows next generation wideband receivers and transmitters to utilize higher levels of dynamic range, which leads to greater receiver sensitivity and transmitter spectral purity. The performance is achieved by the ADF4377 synthesizer delivering jitter levels below 18 fs rms as a consequence of the low normalized in-band phase noise at -239 dBc/Hz, -147 dBc/Hz normalized 1/f noise and a wideband voltage controlled oscillator (VCO) noise floor of -160 dBc/Hz.
The ADF4377 synthesizer is suitable for applications such as radar, instrumentation, and wideband receivers requiring multiple data converters or mixed-signal front-end (MxFE) digitizers to operate together. It significantly simplifies the alignment and calibration routines by allowing groups of data converters to sample their signals in precise alignment with each other. This is fundamental to the operation of next generation ultra-wideband multi-channel systems and is achieved by implementing:
- Automatic reference to output synchronization
- Extremely well-matched reference to output delays across process (3 ps part to part), voltage, and temperature
- Sub-ps, jitter free reference to output delay adjustment capability (+/- 0.1ps)
These features allow for predictable and precise multi-chip clock and SYSREF alignment. JESD204B and JESD204C subclass 1 solutions are supported by pairing the ADF4377 synthesizer with an IC that distributes pairs of reference and SYSREF signals. The ADF4377 integrates all necessary power supply bypass capacitors, saving board space on compact boards.
Key Features of ADF4377
- Output frequency range: 800 MHz to 12.8 GHz
- Jitter = 18 fs rms (Integration BW: 100 Hz to 100 MHz)
- Wideband Noise Floor: -160 dBc/Hz @12 GHz
- PLL Specifications:
- -239 dBc/Hz: Normalized In-Band Phase Noise Floor
- -147 dBc/Hz: Normalized In-Band 1/f Noise
- Phase Detector Frequency up to 500 MHz
- Reference to Output Delay Specifications:
- Part-to-Part Standard Deviation: 3 ps
- Temperature Drift: 0.03 ps/degree
- Multi-chip Output Phase Alignment
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