Freescale Semiconductor has introduced the industry’s first fully software-programmable Digital Front End (DFE) System-on-Chip (SoC) for cellular base station radios. The device virtually eliminates hardware logic design, allowing integrators to concentrate instead on software development and product integration.
The new AFD4400 includes the hardware required to implement a radio’s digital functions in a single device. When combined with Freescale’s extensive reference designs and programming tools, the solution makes radio design easier, faster and more efficient. In addition, the AFD4400 is architected for seamless integration with Freescale’s broad portfolio of second-generation Airfast RF power transistors and RF Integrated Circuits (RFICs), supporting optimal performance in wideband systems ranging from traditional macro base station radios and remote radio heads to small cell base stations and active antenna array systems.
Traditional design processes can slow the development of cellular radios, because solutions based on ASICs and FPGAs require multiple steps: Hardware logic design, followed by software development and product integration. Not only is this complex, expensive and time-consuming, the ASIC approach in particular makes it impossible to rapidly implement changes in wireless standards, frequency bands and signal bandwidths because, once fabricated, the ASIC’s functions are fixed.
The AFD4400 transforms this paradigm by allowing designers to fully program and optimize a radio via software and modify it again with no changes in hardware. Adding frequency bands and modifying RF power levels is simplified as well, as the AFD4400 seamlessly integrates with Freescale’s second-generation Airfast RF power solutions available for virtually all bands worldwide, and supported by reference designs, evaluation boards and other tools.
Its signal processing subsystem leverages an array of vector signal processing cores built on Freescale’s Vector Signal Processor Accelerator (VSPA) architecture. The cores perform virtually all functions using floating-point arithmetic to support the largest possible dynamic range, with an added benefit of accelerating the transition from algorithm development to product realization. The vector processor array is segmented into transmit, receive and adaptation paths with a combined throughput of 3.5 teraflops, providing the performance required to support LTE, WCDMA, CDMA and GSM networks in both single and multi-mode configurations.
The AFD4400 can accommodate 2x2, 4x4 and 8x8 Multiple Input Multiple Output (MIMO) antenna configurations with instantaneous carrier bandwidths up to 100 MHz in four-antenna MIMO configurations, and significantly greater bandwidths in two-antenna MIMO systems. Power control is dynamically applied to individual processing elements, virtually eliminating wasted power in lightly loaded applications.
Extensive Development Tools
Freescale supports the AFD4400 with a comprehensive suite of hardware and software development tools. A development kit includes a modular AFD4400 reference design board (RDB), a choice of several transceiver cards, a shielding chassis, an RF power amplifier reference pallet, host and control software for simplified system setup and configuration, and a quick-start guide.
A comprehensive signal processing reference library eases the transition from hardware-centric to software-based signal processing, while integrated reference application software, optimized for Freescale’s Airfast RF power amplifiers, enables rapid evaluation of DPD performance over most cellular frequency bands and RF power levels. The library includes a wide selection of filter functions, an interpolation/decimation building block, FFT/IFFT functions, LLS/RLS algorithms, crest factor reduction, and DPD subsystems up to 983 MSPS. The signal processing library is augmented with bit-exact MATLAB® functions to enable rapid system prototype simulations during algorithm development and integration.
Freescale’s CodeWarrior Development Studio provides a comprehensive, Eclipse-based software development environment for the VSPA signal processing cores. It includes an optimizing compiler, assembler, linker and cycle accurate instruction set simulator.
