At the 2019 International Solid-State Circuits Conference (ISSCC2019), imec has presented a compact, highly linear 3.2 giga-sample-per-second (GSps) RF-sampling ADC that uses ring amplification (ringamp). The ADC has a record low power consumption of 61.3mW and supports multiband operation and massive MIMO implementation – two key features of future 5G base stations. A second power-efficient ringamp-based ADC – reconfigurable between 6 and 600Msps – was developed for mobile handsets.
Key performance merits of the 3.2 GSps RF-sampling ADC are its excellent spectral purity in combination with a record low power consumption of 61.3 mW – a factor 10 improvement compared with state-of-the-art-technology. The high sensitivity and linearity are demonstrated by the ADC’s Nyquist signal-to-noise-and-distortion ratio (SNDR) of 61.7 dB and by its spurious-free dynamic range (SFDR) of 73.3 dB. The device is fabricated in 16nm CMOS technology and occupies an active area of only 0.194 mm2 (360µm x 540µm). With these record-breaking specifications, two main challenges for future 5G base station ADCs are addressed.
With current base station radios – typically implemented with a zero-IF architecture – multiband operation can only be achieved by implementing an increasing number of transceivers. This significantly contributes to the area and power consumption of the base station. With sampling speeds in the GHz realm, imec’s new ADC allows the development of compact radios that combine multiple bands for cellular infrastructure applications, at much lower power consumption.
Moreover, the large-scale antenna arrays required for MIMO operation are implemented by using a large number of power-hungry discrete transceivers. This RF-sampling ADC fabricated in scaled process technologies, enables massive-MIMO implementation as a System-on-Chip at much lower power consumption and significantly reduced Bill-of-Materials.
At the heart of imec’s RF-sampling ADC is a ringamp-based pipelined architecture. This new amplifier topology offers excellent speed and power efficiency in scaled FinFET technology, allowing fast and accurate settling of large capacitive loads over near-maximum voltage swings in a low supply voltage. It has been combined with a new event-driven approach to timing control in the pipelined ADC architectures that allows for fully dynamic operation of the ADC, where the active blocks only consume power proportional to clock speed.
To demonstrate the versatility of this approach, a second ringamp-based ADC with 6-to-600Msps single-channel speed was developed for mobile handset and smartphone applications. It achieves an ENOB performance of 9.7bit at a Walden figure-of-merit of 12fJ/conv-step. The ADC offers a power-efficient alternative to multi-channel SAR architectures, without the overhead of interleave calibration. Being reconfigurable, the ADC can support a multitude of wireless communication standards and channel bandwidths.
