At DesignCon 2020, Anritsu, is providing design engineers with a portfolio of advanced signal integrity solutions. They are demonstrating test instruments and emerging techniques to verify designs featuring PCI Express (PCIe) 3.0/4.0/5.0, Ethernet PAM4, and other high-speed interconnect technologies to help engineers gain confidence in the chipsets, cables, interconnects and systems being developed.
Headlining the test demonstrations in the Anritsu DesignCon booth is a new PCI Express test solution that supports the PCIe 5.0 Base/CEM Specification Stressed Receiver Test. At the center of the demonstration is the Signal Quality Analyzer-R MP1900A Series with installed Automation Software for base specification calibration and BER Measurement Software supporting the SKP Filter. With the system, engineers can easily configure a measurement environment for early-stage development of PCIe 5.0 IP and devices, expediting the rollout of technology.
The MP1900A is being featured in other demonstrations on verifying high-speed designs. It is integrated with the BERTWave MP2110A and MS9740B OSA to conduct 400G optical PAM4 TDECQ tests, as well as in a configuration to conduct automated high-speed serial bus RX tests.
Also on display at their booth is the ShockLine MS46524B 4-port VNA that conducts de-embedding and network extraction measurements. The VNA is also displayed in a 110 GHz signal integrity measurement configuration for more efficient device modeling.
Technical Sessions at DesignCon 2020
Further discussion on conducting accurate evaluations of high-speed designs will be held on Thursday, January 30, in Great America – Room 2. Anritsu will lead a series of technical sessions addressing emerging test considerations, including:
Characterizing O/E Components – This One session discusses techniques to accurately characterize opto-electronic (O/E) and electro-optical (E/O) components, considered the building blocks of communication systems, and crucial elements for next-generation networks to work seamlessly.
PCIe 4.0/5.0 Tx/Rx LEQ Compliance Test – Held in conjunction with Teledyne LeCroy, the talk gives engineers an understanding of the PCIe test specifications, detailed test procedures, and optimal test equipment configurations to ensure their products pass PCIe 3.0/4.0 TX/RX compliance testing. A PCIe 5.0 test solution will also be introduced.
PCIe 4.0/5.0 SerDes Test – This session discusses how PCIe addresses challenges associated with making 32 GT/s function with NRZ signaling. It will include descriptions of the technology complemented with detailed guidance through the crucial SerDes tests.
400G BER and Jitter Tolerance Test for 53 Gbaud PAM4 with FEC – Anritsu will present the latest test techniques and requirements of the PAM4 400GbE standards. The focus will be on 100G PAM4 signal integrity, jitter tolerance test, ISI injection/emulation, and error distribution analysis to determine how error(s) can be corrected by FEC (Forward Error Correction). Subsequently, Anritsu will conduct a live demo of 100Gbps PAM4 BER and FEC Error Analysis.
Click here to view more highlights from DesignCon 2020.
