Advanced PCB Rule Checking for Signal Integrity and EMC

Patrick DeRoy completed his M.S. (2012) degrees in Electrical Engineering from the University of Massachusetts Amherst. His Master’s work focused on cable shielding and transfer impedance modeling using CST STUDIO SUITE and validating simulation results with measurements. He is Application Engineer at CST of America, supporting customers modeling EMC problems including ESD, radiated emissions and BCI. He is also interested in the simulation of PCBs and mitigation of EMI for such structures.

The performance of a printed circuit board (PCB) for signal integrity (SI) and electromagnetic compatibility (EMC) is mostly based on the placement of components and the routing of signal nets and their power/ground planes. Manual checking of all the various layers of today’s high speed circuit boards is too time consuming and prone to human error. Rule checking software has proven to be a valuable aid for engineers in today’s fast paced design process. It relieves the tedium and removes the human error by rigorously analyzing the geometry of the PCB against a set of rules. All detected rule violations can typically be visually highlighted within such a tool. 

In this webinar we will explore the usage of CST BOARDCHECK on a realistic PCB. Upcoming functionality in CST BORADCHECK will vastly simplify and automate the rule checking workflow by allowing users to define checks based on signal specifications for different types of electronic applications. We will show that for a particular trace layout, a certain signal type may be acceptable whereas another one can cause EMC issues. With the tight integration of CST BOARDCHECK into the CST STUDIO SUITE we will further analyze the detected violations using 3D full wave simulations. The powerful visualization capabilities of the 3D analysis in CST MICROWAVE STUDIO will be used to explain the cause of the violations and also allow us to discuss mitigation strategies.