Design and Simulate Mixed-Signal Front-End and RFDAC Sampling Clocks with Easy to Use Software

Mixed-signal front-end (MxFE) products are enabling the latest software designed radio solution with a very wide 7.5 GHz bandwidth. The digital-to-analog converter (DAC) and analog-to-digital converter (ADC) cores of the MxFE use sampling clocks that originate from either the internal phase locked loop (PLL) or an external clock source. Determining the clock solution is quickly determined using a PLL synthesizer design and simulation tool such as ADIsimPLL™ Designers using the MxFE can now take advantage of the MxFE models recently available in ADIsimPLL to design the high performance sampling clock required for the radio solution, where key performance specifications can be measured, loop filters are optimized, and PLL parameters are adjusted. This article describes the use of this software to model the on-chip PLL and VCO integrated in the MxFE and radio frequency DAC (RFDAC).