Removing Excess Heat from Ungrounded Surface Mount Devices

Ungrounded components don’t have a path to remove heat built in. In tightly packed boards this can cause hot spots and reduce the life and functionality of components. This study will investigate using a thermal pipe to electrically isolate the component while providing a thermal conduction path to the ground.

Introduction

An unwanted byproduct of any electric circuit is the generation of heat, which sometimes requires complex or expensive thermal management solutions. Components without a path to ground to dissipate that heat are constant problems in the electronics industry. These components cause the ambient temperature around them to increase which lowers the life expectancy of all components at this higher ambient temperature. Many solutions to this problem exist including mechanical design changes to increase airflow onto high power components to reduce their overall temperature.

As many circuit designs become smaller, with smaller components packed into a denser area, board space is a premium.  This makes it more difficult to implement large mechanical solutions that control airflow around parts. While many electronics are pushing solutions to lower power consumption to save on energy usage and increase battery life, the increased density continues to push heat to a problematic level.

The proposed solution to this problem is the introduction of ceramic heat bridges. Ceramic heat bridges offer a unique advantage in that they are thermally conductive while remaining electrically isolated. This combination would allow a path for heat to be transferred from a component to the ground or an external heat sink while keeping the component electrically isolated from the ground. While this solution will add an extra component, they are small and combined with heat reduction benefits will make it an economical solution.

Baseline Tests

A resistor was used to emulate the heat output of an ungrounded component on a board. The test board was designed with one resistor that would have different power levels applied across it. The resistor would remain at that power level until temperatures stabilized, at which point the data would be recorded. Power to the test structure was incrementally increased until the resistor reached 125°C.

Figure 1 (top left) shows the resistor on a test board. For the initial test, Bourns CMP2010AFX-1001ELF 1k Ω 1% 1W resistor was chosen as the baseline resistor. The bottom left has the resistor reaching 123°C when 841 mW is applied.

Fig. 1 Top Left Standalone resistor on test board without heat mitigation; Bottom Left Standalone resistor with 841 mW applied; Top Middle Standalone resistor on test board with surface metal heat sync; Bottom Middle Resistor with surface heat sync with 841 mW applied; Top Right Resistor with 2010 ceramic heat bridge; Bottom Right Resistor with 2010 ceramic heat bridge with 841 mW applied.

Holding the standalone resistor constant; different surface mount techniques to dissipate heat were compared to determine the ideal solution with minimal board space. First, it needs to be determined the degree to which extending the pad of the resistor on one end to make a metal heat sink on board will help to reduce heat and increase the power handling of the resistor.

The pad size was determined to match the size of adding a second EIA 2010 size component to the board as shown in Figure 1 (top middle). The heat sink used is ungrounded and open to the room temperature air. No additional airflow was added to help remove heat from the metalized pad. With those conditions, the same test was applied. As shown in the bottom middle, the temperature at 841 mW applied power dropped from 123°C to 106°C. This method is an easy and effective way to help spread the heat generated from an ungrounded part through a wider area of the board

The next step was to use a ceramic heat bridge and repeat the test. For this experiment, the Kyocera-AVX Q-Bridge was used. Part number QB2010A60WS was selected to match the same board space used by the metal pad. Figure 1 (top right) shows the heat bridge connected to one end of the resistor. The other end of the heat bridge is connected to a pad with vias to the backside of the board. The metal on the backside of the board is isolated from the pads that apply power to the resistor and is only used as a heat sink. The resistor remains isolated from the ground, identical to previous tests. Using the same setup as the other baseline tests, the temperature at 841 mW power applied was determined to be 78°C, see the image on bottom right.

Using the collected data at various power levels, the data was plotted, and a best-fit line was determined showing the decrease in temperature at a set power level using the different heat mitigation techniques, as shown in Figure 2.

Table 1: Baseline thermal management test results

Based on the test results, the temperature dropped from 123°C to 78°C by adding a ceramic heat bridge to the ground layer while keeping the resistor electrically isolated. The power handling at 125°C was 0.84 W with no added heat mitigation techniques, 1.04 W with a large, metalized heat sink on the surface of the board, and 1.53 W with a ceramic heat bridge.

Fig. 2 Measured temperature vs applied power and trendlines for baseline testing

Design Optimization Testing Using Heat Bridge

A. Via Density

Fig. 3 Test boards with different vias illustrating the via placement when stepping from 2, 4, to 9 total vias

The baseline test was repeated to determine what the ideal number of vias in the pad to the heat sink would be. For this study, the via size remained the same diameter of 0.3 mm and were filled plated vias. The number of vias varied from 2 to 4, to a maximum via density based on the minimum spacing of vias at the board house used of 0.38mm. For this test, the maximum number of vias was 9. Figure 3 illustrates the via placement on the pad. The pad size remained constant for all of these tests, only the number of vias changed. For this round of testing an EIA 1111 sized heat bridge was used (Kyocera-AVX QB1111A40ES).

The chart in Figure 4 shows that the via density is key to optimizing performance through the heat bridge. While there is marked improvement in jumping from no heat bridge to using a heat bridge with minimal vias, there is improvement to be gained as the heat flow from the surface to the backside increases. Based on this, it is recommended to maximize via density for the pad size when using a heat bridge.

Fig. 4 Measured temperature vs applied power with fixed resistor and ceramic heat bridge, while changing the via density

1) Heat Bridge Geometry Optimization

The next test to complete was to determine what the ideal geometry of the heat bridge would be. There were multiple tests that were completed to determine the optimal results.

2) EIA 2010 Resistor with Fixed Number of Vias

Using the same Bourns CMP2010AFX-1001ELF 1k Ω 1% 1W resistor from the baseline tests, three different test setups were used. It was arbitrarily decided to use two vias for all setups to reduce the number of variables in the geometry optimization test.  This is not the ideal setup for optimal heat extraction, as determined by the previous testing, but again will reduce the number of variables in the test. Three different sizes of heat bridges were used for the test, see Table 2.

Table 2: Heat bridges and test board conditions used for 2010 geometry testing

The initial baseline test was repeated using different Q Bridges from Kyocera-AVX. These different thermal bridges have different recommended pad sizes for solderability. Devices with dissimilar geometries were selected which had different ratios of lengths, widths, and heights that would lead to different cross-sectional areas and total volume.

Figure 5 (left) depicts the measured temperature at 0.87W is 89.3°C, for an EIA 2010 Q Bridge. When the geometry is reversed from a heat bridge that is an EIA 2010 part to an EIA 1020 part, the recommended pad size increases for solderability.  In addition, the cross-sectional area increases for improved heat flow, but the thickness of the part is reduced, causing the overall volume to decrease. The width of the heat bridge is also changing to be larger than the resistor in question. With an applied power of 0.87 W the measured temperature of the resistor increases from 89.3°C to 91.7°C with the reversed geometry 1020 Q-Bridge as shown on the right of Figure 5. The testing continued with the 1111-sized component.

Fig. 5 Left 2010 Resistor with 2010-sized thermal bridge; Right 2010 resistor with 1020-sized thermal bridge

The result of the test shows that the performance is similar between the devices with different geometries at a fixed number of vias, and the trendlines of the collected data across power (Figure 6) corroborate this conclusion. The differences in pad size, cross-sectional area, total volume, and width mismatches have a negligible impact between the 2010 and 1020 options, while the 1111 option has the smallest cross-sectional area, volume, and pad size and expectedly lags the other options slightly.

Fig. 6 Trendline for test results of 2010 resistor heat bridge geometry test

3) EIA 1225 Resistor with Fixed Number of Vias

To help better match the contact surface of the width of the reverse geometry 1020-sized thermal bridge to the 2010 resistor,  a KOA Speer WK73R3ATTE1001F 1.5 W, 1 kΩ, 1% thick film resistor was selected. A new baseline for this resistor needed to be established. Figure 7 (top left) shows that with a power applied of 1.16 W the measured temperature is 127°C. With the baseline established to be 1.16 W without any thermal management, the testing was repeated using the different Kyocera-AVX Q Bridge products listed in Table 3.

Table 3: Heat bridges and test board conditions used for 1225 geometry testing

For this testing, the 1020 and 2525 heat bridges will be closest to matching the width of the 1225 resistor while the 2010 will be held at the center of the resistor and be approximately half the width. The 2010 resistor will match the pad of the 2525 Q Bridge to determine if there is a benefit to the board pad being larger than the heat bridge’s termination.

Fig. 7 Top Left Baseline standalone 1225 sized resistor; Bottom Left 1225 Resistor with 1020 thermal bridge; Top Right 1225 Resistor with 2010 thermal bridge; Bottom Right 1225 Resistor with 2525 thermal bridge

Fig. 8 Trendline for test results of 1225 resistor heat bridge geometry test fixed number of via

Adding a 1020 Q Bridge with 2 vias drops the temperature at 1.16 W from 127°C to a measured 81.2°C (Fig. 7, bottom left).  When the Q Bridge was changed to the 2010 variety the resulting temperature dropped again to 76.5°C (Fig. 7, top right).  When the size of the thermal bridge was maximized for the pads above with a 2525-sized component the temperature further dropped to 74.1°C (Fig. 7, bottom right).  The trendline, based on tested data at a variety of power levels, shows the importance of overall volume to help pull out heat from the ungrounded surface mount device in question.

Fig. 9 Trendline for test results of 1225 resistor heat bridge geometry test maximum via density

Based on the trendline data it can be inferred that thermal bridge volume and board pad size are important aspects for the removal of heat.

4) EIA 1225 Resistor with Maximum Via Density for Pad Size

Based on the test results to this point it can be determined that it is important to maximize the volume of the ceramic heat bridge selected, to maximize the pad size for the board space available, and to maximize the via density. If these aspects are combined, repeating the test using a 1225 resistor with the heat bridge devices from Table 3, but with the maximum via density for those pad sizes should display marked improvement over the fixed via results.

Based on the test results the trendline data in Figure 9 shows that the performance of the 2525-sized ceramic thermal bridge was similar to that of 2010 with the fixed number of vias. As more vias are added, it is made clear the significance of the placement of those vias directly under the thermal egress termination of the heat bridge to efficiently draw out heat.

Summary

Heat produced by ungrounded surface mount components remains a problem in the electronics industry.  A novel solution to this problem is adding a ceramic thermal bridge. Based on test results, any ceramic thermal bridge that fits in the board space available will significantly reduce the temperature of a high-heat component.

Further tests concluded that to optimize the heat reduction and maximum power handling out of an ungrounded surface mount component, certain design criteria need to be met. Test results show that the power output of a component can increase up to 155% from 1.16 W to 2.95 W at 125°C if the via density is maximized under the thermal egress termination, the pad under the termination adjacent to the heat source is maximized, and the volume of the thermal bridge is maximized.  Alternatively, it can be viewed that for a given temperature profile, implementing heat bridges increases the inherent reliability of a system by reducing overall thermal stress on sensitive components. Thermal bridges will expand the capabilities of surface mount components and help mitigate thermal concerns of high-density board design. Electrical isolation was mentioned briefly but should not be dismissed as an enabling property of these heat pipes as viable thermal solutions to be placed directly on signal pins of semiconductor devices. This combination of properties found in a heat pipe like the Q-Bridge devices, will allow designers to push the limits of designs further with a minimal impact on board space and design.