What is a PLDRO - Phase Locked Dielectric Resonator Oscillator?

A phase-locked dielectric resonator oscillator (PLDRO) is a type of oscillator that is used in millimeter-wave communication systems, where phase noise performance is of utmost importance. As wireless communication systems are advancing, the system manufacturers and service providers are all trying to transmit more data within the limited frequency resources available. To do so, they are using more advanced modulation techniques such as 16PSK or 128QAM. Generally, the phase noise of the data modulation index and local oscillator are very closely related. Phase noise of the local oscillator must decrease as the modulation index increases.

The phase noise characteristics of a signal are determined by the oscillation method used to create the signal. Typically, a PLL-VCO (Phase Locked Loop-Voltage Controlled Oscillators) or a PLDRO (Phase Locked Dielectric Resonator Oscillator) is used. PLDRO's are most often used in high frequency microwave systems that require strict phase noise characteristics.

PLDROs are used in a wide range of applications including Radar Systems, VSAT/Satellite Communication Systems, Test Equipment, Microwave Transmitters & Receivers, Cable TV Links (CATV), Up/Down Converters, LMDS, Missile Guidance and Local Area Networks (LAN).

Image 1: Role of local oscillator in the microwave communication system

Image 2: Relationship between phase noise and EVM in 64QAM. It shows that EVM worsens as phase noise deteriorates.

Types of PLDROs

PLDROs can be categorized into several types by the number of frequency lock loops. 

Single Loop PLDROs

Single Loop PLDROs are categorized into PLDROs that use a low reference frequency signal like in Image 3 and PLDROs that use high reference frequency signal like in Image 4. PLDROs that uses low reference frequency signals utilize the method of supplying the Step Recovery Diode (SRD) with appropriate frequency after multiplying the REF_IN signal through the internal frequency multiplier. On the other hand, PLDROs that use a high reference frequency signal, directly supply the SRD with the REF_IN frequency without the internal frequency multiplier.

Image 3: Block Diagram of Single Loop PLDRO using low reference signal

Image 4: Block Diagram of Single Loop PLDRO using high reference signal

The Phase difference between the harmonic components generated based on the standard signal input in SRD and coupled signal from RF_OUT is supplied to the loop filter & search/acquisition block. The voltage corresponding to the phase difference from the loop filter & search/acquisition block is applied to the varactor diode of vt-DRO(Voltage Tuned-Dielectric Resonator Oscillator) block. The frequency is controlled by the bias voltage on varactor diode, the phase lock is maintained for the RF_OUT signal which becomes an integer multiple of the REF_IN signal.

The Single Loop PLDRO provides an ultra-low phase noise of typically -120 dBc/Hz at 100 KHz frequency offset from an output frequency of 10 GHz when it is phase locked to an external 100 MHz crystal reference signal with low phase noise. In addition, two reference options are available. The first option is the Signal Loop PLDRO – High Reference with 50 MHz~500 MHz external reference signal and the second option is the Signal Loop PLDRO – Low Reference with 5 MHz~50 MHz external reference signal.

Single Loop Digital-PLDRO

Signal Loop Digital PLDROs are categorized into those that use a high frequency reference signal like in Image 5 and those that use a lower frequency reference signal like in Image 6.

Digital-PLDRO's that use an external 100 MHz (Higher Frequency) reference signal utilize an internal regenerative frequency divider to divide the 100 MHz REF_IN signal in to a 50 MHz signal which is supplied to the SRD (Step Recovery Diode). Digital-PLDRO's that use the 10MHz (Lower Frequency) reference signal utilize an internal frequency multiplier to multiply the 10 MHz REF_IN signal into a 50 MHz signal to supply which is fed to the SRD. Providing of prime number output frequencies and a very fine frequency resolution that is not supported by single loop PLDROs can be made possible by shifting the phase of the coupled signal from the RF_OUT frequency to become an integral multiple of 50 MHz through the DDS (Direct Digital Synthesizer) and mixer. The phase synchronization method is identical to the above single loop PLDRO.

Image 5: Block Diagram of Single Loop Digital-PLDRO using External 100MHz Reference

Image 6: Block Diagram of Single Loop Digital-PLDRO using External 50MHz Reference

Because a VCXO (Voltage Controlled Crystal Oscillator) is not used in this Single Loop Digital-PLDRO, it has the advantage of being able to develop products of various frequencies at a lower cost in a shorter period of time compared with Dual Loop PLDRO using VCXO.

Dual Loop PLDRO

Dual Loop PLDRO is a PLDRO used to generate an output frequency that is not an integer multiple of external reference signal frequency. Typical dual loop PLDROs consists of two loops as shown in Image 7; the first loop is used to provide the reference frequency to the second loop.

REF_IN, the external reference signal, is amplified to an appropriate level and input to the SRD (Step Recovery Diode). The phase difference between harmonic component generated from signal standard inputted in SRD and coupled signal from the coaxial resonator is provided to the loop filter & search/ acquisition. A voltage corresponding to the phase difference from loop filter & search/ acquisition block is applied to varactor diode of vt-CRO(Voltage Tuned-Coaxial Resonator Oscillator) block. The frequency is controlled by the biased voltage on varactor diode, the phase lock is maintained and outputted for the vt-CRO output frequency to become integer multiple of REF_IN. The phase locked output signal of the first loop is divided into an appropriate frequency by the frequency divider to be used as a standard signal in the second loop. The action of the second loop is identical to above single loop PLDRO.

Image 7: Block Diagram of Dual Loop PLDRO