Realtek has adopted a leading-edge and user-friendly electromagnetic (EM) simulation workflow developed by Ansys to accelerate complex RFIC design and improve efficiency by shrinking the silicon area. Realtek uses RaptorH's silicon-optimized modeling flow to substantially decrease simulation time and reduce wasteful overdesign by accurately predicting EM coupling in applications ranging from RFIC and high-speed IC to cutting-edge Internet of Things products.
RFIC advanced node designs must manage the growing challenge of EM interference caused by high-frequency, millimeter wave signals and occurring across different RF blocks. To improve the efficiency of design margins, Realtek IC designers rely on Ansys® RaptorH™'s large capacity engine to analyze complete circuit blocks with high fidelity.
By adopting this silicon-optimized modeling flow, Realtek designers are accelerating EM modeling times by 3x – 10x. Additionally, they are shrinking silicon real estate by drastically reducing block-to-block EM crosstalk in extremely complex designs.
"RaptorH delivers a highly intuitive graphical user interface with a simplified setup that does not require any manual modifications to the layout or foundry tech files for performing EM coupling analysis," said Yee-Wei Huang, Vice President at Realtek. "It helped our engineering team identify EM coupling problems in our on-chip design flow. This predictive accuracy, together with its high capacity and speed, enabled our designers to minimize area and increase the value without compromising fidelity in new, extremely complex chips."
John Lee, Vice President and General Manager of the electronics and semiconductor business unit at Ansys, said that RaptorH plays an integral role in their industry-leading, gold standard simulation platform for modeling EM and multiphysics interactions across the latest generation of IC layout structures. Providing an optimum user experience and delivering reliable results, this product's cutting-edge S-parameter and reduced SPICE models help Realtek designers capture the behavior of very high-frequency signals to solve complex IC layout problems with increased confidence, resulting in more efficient and reliable products.
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