Cadence Design Systems, announced that its digital and custom/analog design flows have been certified for the TSMC N3E and N4P processes, supporting the latest Design Rule Manual (DRM). In addition, Cadence and TSMC delivered N3E and N4P process design kits (PDKs) and design flows to accelerate customer adoption and advance mobile, AI and hyperscale computing design innovation. Joint customers are actively designing with the new N3E and N4P PDKs, and several test chips have already been taped out, which demonstrates how Cadence solutions help customers improve engineering efficiency and maximize the power, performance and area (PPA) benefits offered by the latest TSMC process technologies.
Cadence announced that its digital and custom/analog design flows have been certified for the TSMC N3E and N4P processes, supporting the latest Design Rule Manual, accelerating mobile, AI and hyperscale computing design innovation.
The Cadence digital and custom/analog advanced-node solutions support the company’s Intelligent System Design™ strategy, enabling system-on-chip (SoC) design excellence.
N3E and N4P Digital Full-Flow Certification
Cadence worked closely with TSMC to ensure the digital full flow was optimized for TSMC’s advanced N3E and N4P process technologies. The complete RTL-to-GDS flow includes the Cadence Innovus™ Implementation System, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Signoff Solution and ECO option, Pegasus™ Verification System, Liberate™ Characterization Solution and Voltus™ IC Power Integrity Solution. Additionally, the Cadence Genus™ Synthesis Solution and predictive iSpatial technology are enabled for the TSMC N3E and N4P process technologies.
The digital full flow offers several key capabilities that support the TSMC N3E and N4P process technologies, including the correlation between implementation and signoff results; enhanced via pillar support; efficient handling of large standard cell libraries containing many multi-height, voltage threshold (VT) and drive strength cells; low voltage cell characterization and certified signoff timing accuracy; and certified extraction accuracy with the Quantus Extraction Solution and Quantus Field Solver.
Innovus™ Implementation System :
A physical implementation tool for high-density designs at advanced and established process nodes, the Innovus Implementation System delivers a typical 10%-20% PPA advantage along with an up to 10X TAT gain. Providing the industry’s first massively parallel solution, the Innovus Implementation System can effectively handle blocks as large as 5-10 million instances or more.
Quantus™ Extraction Solution :
The Cadence® Quantus™ Extraction Solution is a next-generation parasitic extraction tool for digital and custom/analog flows. Providing the fastest single-corner and multi-corner runtimes compared to competitive products, the tool features massively parallel architecture for performance and scalability across hundreds of CPUs. Its high-accuracy modeling engine delivers impeccable accuracy that has been silicon proven over thousands of tapeouts to support FinFET and all other designs. It uses one unified, foundry-qualified “qrctechfile” for both digital and transistor extraction. The solution, employing a robust 3D modeling framework, is certified by TSMC for all nodes down to 3nm. In addition, the Quantus Extraction Solution is certified for all nodes at all other leading foundries.
Quantus Field Solver :
Cadence has been working with foundries on creating a field solver solution that has the required accuracy, a run-time that is the same order of magnitude as 2.5D extraction, and keeps the netlist size under control. The product is called Quants FS. Key features are:
- Cloud ready—Scales to 1000s of cores
- Low memory consumption leading to high capacity
- Best-in-class accuracy versus foundry golden data
- Smallest netlist size that speeds up characterization and simulation runtimes
- Certified at all major foundries
- Integrated into other Cadence tools (Innovus, Virtuoso, Liberate, Spectre).
Click here to learn more about Quantus Field Solver.
N3E and N4P Custom/Analog Flow Certification
The Cadence Virtuoso® Design Platform, which includes the Virtuoso Schematic Editor, Virtuoso ADE Product Suite and Virtuoso Layout Suite EXL, the Spectre® Simulation Platform, which includes Spectre X Simulator, Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS) and the Spectre RF Option, as well as the Virtuoso Application Library Environment and Voltus-Fi Custom Power Integrity Solution have achieved the latest TSMC N3E and N4P certifications. One unique capability that the Virtuoso Design Platform offers is tight integration with the Innovus Implementation System, which enhances the implementation methodology of mixed-signal designs using a common database. The Virtuoso Schematic Editor’s migration module in the Virtuoso Application Library Environment has been integrated and verified by TSMC.
The Virtuoso Schematic Editor, the Virtuoso ADE Suite and the integrated Spectre X Simulator have been optimized for the custom design reference flow (CDRF) for managing corner simulations, statistical analyses, design centering and circuit optimization. Furthermore, the CDRF’s Virtuoso Layout Suite EXL has been enhanced for efficient layout implementation, which provides customers with several features, including a unique row-based implementation methodology with interactive, assisted features for placement, routing, fill and dummy insertion; enhanced analog migration and layout reuse functionality; integrated parasitic extraction and EM-IR checks and integrated physical verification capabilities.
“Through our latest collaboration with Cadence, we’re making it easy for customers to benefit from the significant power and performance boosts of our latest N3E and N4P process technologies to drive design innovation forward,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “Our customers have to develop designs at an exceptionally rapid pace to keep up with market demands, and the design flows’ certification gives customers confidence that they can use our technologies to achieve design goals and get to market faster.”
“Our digital and custom/analog flows are packed with features that enable our customers to achieve optimal PPA while improving engineering productivity when creating N3E and N4P designs,” said Dr. Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “By working closely with TSMC, we’re helping customers achieve SoC design excellence across a variety of market segments such as mobile, AI and hyperscale, and we’re looking forward to seeing many successful advanced-node innovations.”
The Cadence Virtuoso® Design Platform :
Vituoso System Design Platform Flow
The Cadence® Virtuoso® System Design Platform is a holistic, system-based solution that provides the functionality to drive simulation and LVS-clean layout of ICs and packages from a single schematic. There are two key flows: implementation and analysis. The implementation flow is used to create an IC package schematic in Virtuoso Schematic Editor and then transfer the schematic data to Cadence SiP Layout to layout the physical design. In addition, this flow offers the capability to generate and verify library parts, output a bill of materials (BOM), and perform layout versus schematic (LVS) checking. The analysis flow is used to extract and simulate any portion of the system (IC-package-PCB) regardless of the layout design status. Moreover, this flow offers the capability to automatically generate schematics for the PCB and IC package layouts, bind the instances of the IC package to the IC schematic or models, and build testbenches to simulate the system using the Virtuoso ADE Product Suite plus Spectre® Multi-Mode Simulation interface. Cadence Sigrity™ models extracted from the PCB and IC package layouts get automatically stitched into the generated schematic.
The Cadence® Spectre® Simulation Platform :
Spectre Simulation Platform
The Cadence® Spectre® Simulation Platform, built on an advanced infrastructure, combines industry-leading simulation engines to deliver a complete design and verification solution. It meets the changing simulation needs of designers by preserving results and IP as they progress through the design cycle—from architectural exploration, to analog and RF block-level development with flexible and reliable abstraction, including memory design, to final analog and mixed-signal full-chip verification for increased productivity and throughput.
Click here to learn more about The digital and custom/analog advanced-node solutions.
Click here to learn more about Intelligent System Design™ strategy.
