IBM is now offering its clients a new set of interoperable PDK's (process design kits) (PDKs) that have been are designed for use with Keysights Advanced Design System (ADS) EDA software and Cadence Design System’s Virtuoso® custom design platform, providing users access to a new silicon RFIC interoperability feature available in ADS 2015.01. The first interoperable PDK is now available for SiGe 5PAe. The 350 nm SiGe BiCMOS process and RF SOI technologies gained significant industry traction for cellular and wifi front-end module applications, and the new silicon RFIC interoperability feature can offer clients using these technologies additional design flexibility.
IBM silicon-based specialty foundry technologies—RF CMOS, RF silicon-on-insulator (SOI), and silicon germanium (SiGe)—are optimized to help chip suppliers deliver differentiated RF front-end solutions in increasingly sophisticated devices. The new Silicon RFIC Interoperability is crucial for IC design and enables a true RFIC/package/board co-design flow. This interoperable flow increases designer productivity and flexibility, and reduces time-to-tape-out for silicon-based RF designs.
The challenges of high frequency and large-signal design in these devices have increased the need for an interoperable co-design flow that exploits the best of both design platforms and that can help maximize designer productivity. The ADS silicon RFIC interoperability feature simplifies this process by enabling users to edit and simulate schematic designs created by the Virtuoso environment in ADS, and vice versa. The same is true for layout where, for example, a user can open a Virtuoso IC layout cell view in ADS, instantiate the cell within a package or module, and then run an electromagnetic simulation on the complete design to validate its overall system performance.
