Cadence Design Systems and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics. This collaboration significantly advances system and semiconductor design for AI, automotive, aerospace, hyperscale and mobile applications and has resulted in the following recent technology achievements:
Cadence and TSMC have worked closely together to release a Virtuoso Studio N16 to N6 RF migration reference flow to substantially reduce turnaround time: Purposed-based instance mapping rapidly retargets schematics, while EMX Planar 3D Solver provides inductor synthesis and EM extraction for nets and components during the design phase. The Virtuoso ADE Suite provides design optimization using Spectre Simulation’s RF analysis capabilities, and Virtuoso Studio Layout tools accelerate the reuse and reimplementation of RF layouts while preserving design intent.
The Cadence Custom/Analog Design Flow is fully certified for TSMC’s latest N2 Process Design Kit (PDK): Cadence custom tools optimized for TSMC N2 PDKs include Virtuoso Schematic Editor for design capturing and the Virtuoso ADE Suite for analysis, which are both part of Virtuoso Studio, and the integrated Spectre Simulator. All have been enhanced for managing corner simulations, statistical analyses, design centering, and circuit optimization, which are now common with advanced nodes. Virtuoso Studio has also been augmented to support front-to-back process migration from schematic mapping to optimized design specifications to full-layout place-and-route automation. The Virtuoso Studio and Spectre Simulation platforms, including Spectre X, Spectre XPS and the Spectre RF Option, have achieved the latest TSMC N2 certifications.
Cadence collaborates with TSMC to infuse the Integrity 3D-IC platform with new features and functionality: The Cadence Integrity 3D-IC platform, the industry’s comprehensive solution certified for all the latest TSMC 3DFabric offerings, now supports a hierarchical 3Dblox specification developed to integrate multiple chiplets into hierarchies for reuse and modular design. It also includes new features developed to ease chiplet assembly and design, and an automated alignment markers insertion flow to accelerate the design and assembly of stacked chiplets on different interposers and packages.
Cadence’s digital solutions are certified for TSMC N2 design flow, including Innovus Implementation System, Quantus™ Extraction Solution, Quantus Field Solver, Tempus Timing Signoff and ECO Solution, Pegasus Verification System, Liberate characterization, and the Voltus IC Power Integrity Solution. The Genus Synthesis Solution is also enabled for N2 technology. Cadence and TSMC are collaborating on AI-driven Cadence solutions to enable an AI-assisted design flow for productivity and optimization of PPA results.
Cadence announces the availability of a comprehensive portfolio of industry-leading IP cores for TSMC’s N3 process, including:
- Cadence’s IP for UCIe on TSMC N3 is available in both advanced and standard package options. Cadence also offers IP for UCIe on multiple processes and configurations to enable a comprehensive solution for die-to-die (D2D) interconnect for its customers.
- The Cadence memory interface IP portfolio (DDR5, LPDDR5 and GDDR6) is silicon-proven with best-in-class system margins and a PPA-optimized architecture that is ready to enable next-generation enterprise, high-performance computing and AI applications.
- Cadence’s IP for PCIe 5.0/CXL2.0 and PCIe 6.0/CXL3.0 on TSMC N3 are designed to provide the highest link throughput and utilization while operating with low latency, providing customers with SoC design excellence.
The Cadence EMX 3D Planar Solver has received certification for TSMC’s N5 process technology: This certification enables joint customers to seamlessly integrate the EMX Solver into their advanced-node IC design flow, allowing for highly accurate EM analysis that can overcome the challenges of EM crosstalk and parasitics. Additionally, certification for N2 and N3 process technology is well underway.
Cadence unveils a new silicon photonics flow to support TSMC’s Compact Universal Photonic Engine (COUPE) technology: Cadence and TSMC collaborate to develop a design flow for the COUPE 3D photonics process that features the Cadence Integrity 3D-IC platform. The TSMC COUPE technology enables the heterogeneous integration of photonics ICs with electrical ICs while minimizing coupling losses. The developing design flow from Cadence will support TSMC’s COUPE technology and includes the Cadence Spectre X Simulator, Virtuoso Studio, EMX 3D Planar Solver and Pegasus Verification System, enabling joint customers to meet the most demanding system requirements and pave the way for high-performance computing applications.
“We have a distinguished track record collaborating with TSMC to deliver a broad set of innovations across EDA, packaging and IP to accelerate system and semiconductor design and enable customers to achieve aggressive time-to-market goals,” said Chin-Chi Teng, SVP and GM, R&D, Cadence. “These new certified design flows and standardized solutions allow customers to confidently design for TSMC advanced nodes and usher in improved design efficiency and technological advancements.”
“TSMC works closely with Cadence to accelerate customer innovation by providing high-quality design tools certified for use with our most advanced processes,” said Dan Kochpatcharin, Head of the Design Infrastructure Management Division at TSMC. “Through our longstanding collaboration, we’re able to deliver greater value for the most advanced SoC designs, benefiting from the significant power and performance boost afforded by our latest technology innovations.”
