The ADRV9040 from Analog Devices is a System on Chip (SoC) RF Transceiver that operates from 650 to 6000 MHz. It meets the high radio performance and low power consumption demanded by cellular infrastructure applications including small cell base station radios, macro 3G/4G/5G systems, and massive MIMO base stations.
The SoC has an integrated digital front end (DFE), eight transmitters/receivers, two observation receivers for monitoring transmitter channels, integrated LO & clock synthesizers, and digital signal processing functions. The Rx and Tx signal paths use a zero-IF (ZIF) architecture that provides wide bandwidth with a dynamic range suitable for contiguous and non-contiguous multicarrier base station applications. The DFE allows carrier digital up/down conversion (CDUC and CDDC), crest factor reduction (CFR), digital pre-distortion (DPD), closed-loop gain control (CLGC), and VSWR monitor. The CFR engine of the ADRV9040 reduces the peak-to-average ratio of the input signal, enabling higher efficiency to transmit line ups while reducing the processing load on baseband processors.
The ADRV9040 includes two wide-bandwidth observation path receiver sub-systems for monitoring transmitter outputs. It includes automatic and manual attenuation control, DC offset correction, quadrature error correction (QEC), and digital filtering. It also contains a fully integrated DPD engine for use in power amplifier (PA) linearization. The DPD enables high-efficiency PAs, reducing the power consumption of base station radios and the number of SERDES lanes interfacing with baseband processors.
The ADRV9040 is powered directly from 1.0, 1.3 & 1.8 V regulators and consumes 13 W of power with all blocks enabled. It is controlled via a standard serial peripheral interface (SPI) port which consists of eight serializer lanes and eight de-serializer lanes. The SoC is available in a BGA package that measures 27 x 20 mm.
