Imec, a leading research and innovation hub in nanoelectronics and digital technologies, is making significant progress in developing the next generation of wireless communication technologies. With the increasing demand for faster and more efficient data transfer, researchers are looking beyond the current fifth-generation (5G) mobile communication to envision the sixth-generation (6G) networks, which are projected to operate at peak data rates of 100Gbit/s from 2030 onwards.
To enable these exceedingly high data rates, the telecom industry has been pushing up the frequencies of wireless signals. While 5G initially uses sub-6GHz frequency bands, products targeting 28/39GHz are already showcased. Additionally, there is a growing interest in using FR3 (6-20GHz) frequency bands for 5G networks due to their ability to balance coverage and capacity.
Moving toward higher frequencies has several advantages: new frequency bands can be used, solving the spectrum scarcity issue within existing bands. Also, the higher the operating frequency, the easier it is to obtain wider bandwidths. Frequencies above 100GHz and bandwidths up to 30GHz allow telecom operators, in principle, to use lower-order modulation schemes within the wireless data links, which reduces power consumption. Higher frequencies are also associated with smaller wavelengths (λ). As the antenna array size scales with λ², antenna arrays can be packed more densely. This contributes to better beamforming, a technique that ensures that a larger fraction of transmitted energy reaches the intended receiver.
But the advent of higher frequencies comes at a price. Today, CMOS is the preferred technology for building the critical components of transmitters and receivers. These include the power amplifiers within the front-end modules that send the radio frequency signals to and from the antennas. The higher the operating frequency, the more the CMOS-based power amplifiers struggle to deliver the required output power with sufficiently high efficiency.
And that’s where technologies such as GaN and InP come into play. Due to outstanding material properties, these III/V semiconductors are more likely to provide the required output power and efficiency at high operating frequencies. GaN, for example, has a high current density, high electron mobility, and large breakdown voltage. The high power density also allows for a small form factor and, thus, a reduction in overall system size at the same performance.
Imec conducted a modeling exercise to compare the performance of different power amplifier implementations at an operating frequency of 140GHz. The results showed that InP-based power amplifiers outperformed CMOS-based and CMOS beamformer with SiGe heterojunction bipolar transistor (HBT) implementations in terms of output power and energy efficiency. GaN-on-silicon-carbide (GaN-on-SiC) high-electron-mobility transistors (HEMTs) also demonstrated excellent performance at lower millimeter-wave frequencies (28 and 39GHz) compared to CMOS-based devices and GaAs HEMTs. In this exercise, two different use cases were considered, i.e., fixed wireless access (FWA, with 16 antennas) and user equipment (with four antennas).
Figure 1 – Comparing the power consumption of CMOS, SiGe, and InP devices in transmitter architectures as a function of the number of antennas (as presented at IEDM 2022).
Figure 2 – Output power for 28GHz and 39GHz operating frequencies in (left) FWA and (right) user equipment: a comparison of three different technologies (as presented at IEDM 2022).
While GaN and InP offer superior performance at higher frequencies, they face challenges in terms of cost and integration with CMOS-based technologies. GaN and InP devices are typically manufactured on small and costly non-silicon (Si) substrates, which limits their scalability for mass production. Imec is exploring the integration of GaN and InP devices on larger Si wafers, which are more cost-effective and compatible with CMOS manufacturing processes.
Integration of GaN and InP on Si substrates requires innovative approaches in transistor and circuit design, materials selection, and manufacturing techniques. One of the main challenges lies in the large lattice mismatch between the III/V semiconductors (InP and GaN) and Si, which leads to defects that degrade device performance.
Imec’s GaN-on-Si process flow for RF starts with the growth (by metal-organic chemical vapor deposition (MOCVD)) of an epitaxial structure on 200mm Si wafers. This structure is comprised of a proprietary GaN/AlGaN buffer structure, a GaN channel, an AlN spacer, and an AlGaN barrier. GaN HEMT devices with TiN Schottky metal gate are subsequently integrated with a (low-temperature) 3-level Cu back-end-of-line process.
Recently, competitive results have been obtained on Imec’s GaN-on-Si platform, bringing the output power and power added efficiency (PAE) for the first time closer to those of the GaN-on-SiC technology. The PAE is a commonly used metric to rate the efficiency of a power amplifier, which takes into account the effect of the amplifier's gain on its overall efficiency.
Figure 3 - GaN-on-Si benchmarking data. The imec data in red is among the best reported for GaN-on-Si devices and comparable to GaN-on-SiC substrates (as presented at IEDM 2022). References: [1] H.W. Then et al., IEDM 2020; [2] H.W. Then et al., IEDM 2021; [3] W. Wang et al., J-EDS 2018; [4] Y.C. Lin et al., Micromachines 2020; [5] M. Mi et al., TED 2017; [6] Y. Zhang et al., EDL 2018; [7] K. Harrouche et al., HAL open science, 2020; [8] J.-S. Moon et al., MTTS 2019.
At an operating frequency of 140GHz, InP heterojunction bipolar transistors (HBTs) have demonstrated the best trade-off between output power and efficiency compared to other technology implementations. However, the fabrication process for InP devices typically involves small InP substrate wafers and non-CMOS compatible processes.
To overcome this limitation, Imec is exploring three approaches for upscaling InP-on-Si technology. The first approach involves depositing strain-relaxed buffer layers directly on Si to compensate for the lattice mismatch between Si and InP. InP is then grown on top of the buffer layer. This method allows for larger wafer sizes, leading to cost advantages, but further optimizations are required to reduce defects.
Figure 4 – Schematic representation of the different InP-on-Si growth approaches: (a) nano-ridge engineering; (b) blanket growth with strain relaxed buffers, and (c) wafer reconstruction.
Another approach, nano-ridge engineering (NRE), selectively grows III/V material in pre-patterned trenches in Si. Defects are trapped in the narrow bottom part of the trenches, enabling the growth of high-quality InP material. The nano-ridge is then overgrown to form a solid base for device stacking. Imec is using insights from a GaAs/InGaP case study to optimize InGaAs/InP NRE HBT devices.
Figure 5 – A two-inch InP wafer, and a 300mm Si wafer with a InP NRE HBT stack.
The third approach involves wafer reconstruction, where high-quality InP substrates are diced into tiles and bonded to a Si wafer. Efficient material transfer and InP substrate removal are key challenges in this method.
Integration of III/V-on-Si power amplifiers with CMOS-based components is crucial. Imec is exploring various heterogeneous integration options, including advanced laminate substrate technology, 2.5D interposer technology, and 3D integration technologies. These integration techniques aim to combine different RF components, optimize performance, and address thermal management concerns.
For frequencies above 100GHz, the size of the antenna array becomes a limiting factor. Imec proposes moving the RF front-end module under the antenna array using 3D integration technologies, allowing for short and well-defined connections. However, thermal management remains a challenge, and effective heatsinks are being developed.
In handheld devices, where fewer antennas are required, 2.5D interposer technology offers an interesting approach. It involves lithography-defined connections and through-Si vias to communicate between III/V- and CMOS-based components. This architecture allows for better thermal management and enables 1D beam steering. Imec is currently evaluating hardware implementations of 2.5D interposer technology, looking into the most optimal combinations of substrates, dielectrics, and redistribution layers to minimize losses. They have shown a first version of an RF-tailored Si interposer technology using a standard Si substrate, copper semi-additive interconnect, and thick spin-on low-k dielectrics that exhibit very low interconnect loss, even above 100GHz.
Figure – Schematic representation of an RF Si interposer with integrated InP and CMOS devices and antenna array in a package.
Recent upscaling and integration efforts show that GaN-on-Si and InP-on-Si can become viable technologies for next-generation high-capacity wireless communication applications.
Click here to learn about the advantages of GaN on SiC.