Synopsys and Helic have announced a joint collaboration to integrate the Helic VeloceRF - RF device synthesis, RaptorX - EM modeling, Exalto - EM parasitic extraction and signoff tools with Synopsys' Custom Design Platform. The result of the collaboration is a complete solution for electromagnetic-aware (EM-aware) layout and analysis of mixed-signal, analog, and RF designs.
The Synopsys/Helic EM-aware flow provides a GUI within the Custom Compiler for users to generate DRC-clean layouts of single- or multi-inductor spiral structures with VeloceRF. VeloceRF also creates schematic symbols and simulation models that are ready for use in the Custom Compiler, and LVS rules for verification of the generated devices with IC Validator. The flow also includes a tight integration of Helic's RaptorX, for in-design analysis of EM effects during layout. Early awareness of EM effects helps reduce iterations during signoff verification. The Exalto EM parasitic extraction engine works with Synopsys' StarRC tool to provide a complete RLCK parasitic netlist that is ready for RF simulation. Synopsys Custom Design Platform users can perform frequency-domain simulation of their circuits with HSPICE technology and analyze the results with the Custom WaveView solution.
Designers of chips operating at high data bandwidth and frequencies need detailed parasitic extraction and EM-aware analysis early and throughout the physical design flow. Bringing EM-aware modeling, analysis, and signoff technology into the Synopsys Custom Compiler environment will enable mutual customers to avoid excessive margining and guard-banding and reduce the risk of silicon surprises.
Click here to learn more about Helic VeloceRF.
Click here to learn more about Helic RaptorX.
Click here to learn more about Helic Exalto.
